We would like you to have 3+ years of relevant experience in RF, including solid expertise in cellular PLL architectures.
You have extensive experience in specifying, simulating and modelling PLLs and LO distribution including the mathematical background.
You have strong understanding of frequency generation architectures, experience in analyzing crosstalk and coexistence scenarios and avoiding or mitigating them.
You have in-depth knowledge of cellular radio standards (GSM, UMTS, LTE, 5G NR), regulatory, and carrier requirements including their implications on PLL specifications.
Excellent communication skills, both written & verbal, would be very helpful.
In this role, you will be part of the best-in-class cellular RFSE Team. You will work closely with transmitter and receiver architecture teams, RF design teams, design and drive PLL innovations with focus on leading-edge performance under real-life conditions and clear differentiation from other solutions.
YOUR DAILY WORK INCLUDES THE FOLLOWING TASKS : - Defining and specifying PLL and clocking architectures for FR1 and FR2 (mmW)- Break-down PLL system requirements into requirements for the PLL building blocks including phase noise budget.
Implementation and simulation of the PLL in the frequency-domain and in the time-domain using MATLAB and C++.- Develop algorithms to improve PLL phase noise performance and methods to reduce spurs.
Prepare specifications as input for design teams.- Implementation of bit-true MATLAB and C++ reference models for the digital design.
Align MATLAB and C++ models with measurement results.
Education & Experience
MSEE is the foundation of your successful career to date. We would prefer a Ph.D. in electrical engineering or equivalent.