We support a renowned high-tech company in the Vienna area with their search for a Senior Verification Engineer (m / f).
As a Senior Verification Engineer you bring :
a university degree in electrical engineering or similar
at least 5 years of experience in the verification of ASICs or FPGAs
solid background in developing UVM-based SystemVerilog testbenches
knoeledge of scripting languages (Shell, Python, Persl, TCL)
As a Senior Verification Engineer you will :
create and execute verification plans for complex ASICs and FPGAs
develop verification environments in UVM / SystemVerilog
establish and improve the verification infrastructure
If this job as a Senior Verification Engineer attracts your interest and suits your background, please get in contact with Nicole Lamprecht for more information.